A process for creating an etch mask having feature widths less than the resolution capability of available photolithography is disclosed in a copending U.S. patent application submitted by Tyler Lowrey and Randal Chance of Micron Technology, Inc. The application, entitled "Method for Reducing by a 2.sup.-N the Minimum Masking Pitch of a Photolithography Process used in the Fabrication of an Integrated Circuit", was filed on May 7, 1990 and assigned Ser. No. 07/519,992. The process makes use of edge definition (thin vertical film layer segments created using an anisotropic spacer etch) to create a hard-material (silicon dioxide) mask consisting of substantially parallel stringers (spacer strips), each of which is half the minimum feature width (F) of the available photolithographic process. The stringers are separated, one from another, by gaps which are also equal to F. The process may be further replicated in order to create masks with stringers having feature widths of 1/4F., 1/2F., and so on. The Lowrey-Chance reduced-pitch masking process has been incorporated into a process sequence for creating an ultra-dense dynamic random access memory array which is the subject of U.S. Pat. No. 5,013,680, which was originally filed July 18, 1990 as applicatioon Ser. No. 07/555,980, and is entitled "Process for Fabricating a DRAM Array Having Feature Widths that Transcend the Resolution Limit of Available Photolithography". The process, developed by Tyler Lowrey, Randal Chance, Mark Durcan, Ruojia Lee, Charles Dennison, Yauh-Ching Liu, Pierre Fazan, Fernando Gonzalez and Gordon Haller (all of Micron Technology, Inc.), utilizes the Lowrey-Chance masking process for creating a hard-material mask that is used to anisotropically etch a series of parallel isolation trenches in a silicon substrate. The DRAM fabrication process also requires the creation of a second hardmaterial mask, having feature widths equal to 11/2F. separated by gaps equal to 1/2F., that is used to anisotropically etch a matrix of storage trenches. Each hard-material strip of the first hard-material mask has one rounded shoulder, while each hard-material strip of the second hard-material mask has rounded shoulders on both edges. Round-shouldered edges on masking strips is responsible for a certain amount of ion reflection during a plasma etch that, under certain conditions, may lead to the etching of irregularly-shaped trenches.
With the aim of reducing plasma particle reflection from the rounded shoulders of the hard-material strips which comprise the aforementioned hard-material masks, Mark Durcan and Ruojia Lee, two of the aforementioned inventors, developed a process for rectangularizing asymmetrical silicon dioxide spacer strips. The process has been disclosed in a copending U.S. patent application entitled "Method for Rectangularizing Asymmetrical Spacers in a Process for Reducing Minimum Masking Pitch", that was filed on May 10, 1990 and assigned serial No. 07/526,079.
Silicon dioxide has become the preferred hard-mask material for anisotropically etching trenches in silicon, and as heretofore explained, the hard-material etch masks used to create the ultra-dense DRAM array are preferably created from silicon dioxide. In a chemically-halogenated plasma (the standard environment for such etches), silicon dioxide has a reactivity (also termed "selectivity") approximately 1/40 to 1/10 that of silicon. In other words, a silicon dioxide etch mask is subject to a certain amount of erosion during the etch step. For a given mask thickness, mask selectivity effectively limits trench depth. At the high end of the selectivity range, it is necessary to alter the chemistry of the plasma with chemical species that tend to cause deposition of unwanted materials on the surfaces of the etch chamber. For example, the presence of oxygen radicals and ions, chemical species that enhance selectivity of silicon over oxide during a halogenated-plasma etch, react with the silicon substrate to form silicon dioxide that is deposited as a glass layer on etch chamber walls. Deposited materials represent a potential source of pollution that must be periodically removed from the chamber. In addition, since mask selectivity may also be etch-rate dependent, it may be necessary to perform a plasma etch at an inconveniently slow rate in order to achieve a desired trench depth with an oxide mask of optimal maximum thickness. Additionally, as silicon dioxide masking material is eroded during a plasma etch, it may be redeposited on trench sidewalls near the trench mouth, further complicating the fabrication process. Finally, if MOS gates have been created prior to an anisotropic plasma etch, removal of a silicon dioxide patterning mask with an isotropic oxide etch subsequent to the trench etch may compromise the integrity of existing gate oxide. This is especially true at gate edges.
Recognizing the need for an etch mask that would permit cleaner etching environments and that would not significantly erode during an extended halogenated-plasma etch required for deep trenches, David Cathey and Trung Doan of Micron Technology, Inc., developed a metal masking process that is the subject of U.S. Pat. No. 5,001,085, which issued on Mar. 19, 1991, and is entitled "Process for Creating an Erosion-Resistant Metal Etch Mask for HalogenPlasma Excavation of Deep Trenches". This patent matured from application Ser. No. 07/554,630, which was filed on July 17, 1990. Masks are created from either cobalt, nickel, palladium, iron or copper, with react with silicon at elevated temperatures to form a metal silicide, which have melting points appreciably greater than 850.degree. C. (the approximate temperature at which polycrystalline silicon is normally deposited), and which do not react with chlorine, fluorine, or bromine to form volatile compounds with boiling points below approximately 300.degree. C. (a necessary criterium for a material to be immune to erosion during a halogenated-plasma etch). The masking process begins by creating a thin isolation layer of either silicon nitride or silicon dioxide (preferably the latter due to the perforation defects common to a deposited nitride layer) on top of the layer to be etched (typically a silicon substrate). A thin layer of one of the metals selected from the aforementioned list of five is then deposited on top of the isolation layer. A layer of polysilicon is then blanket deposited on top of the metal layer. The thickness of the polysilicon layer must be at least sufficient to entirely consume the metal layer when silicide-forming temperatures are reached. Photoresist masking is then performed as though the photoresist were the actual pattern for the desired trench etch. Exposed portions of the polysilicon layer are then etched away, preferably with an anisotropic etch in order to protect the polysilicon layer from undercutting. Following a photoresist strip, the substrate and overlying layers are subjected to an elevated temperature step, which causes the polysilicon to react with the underlying metal layer to form metal silicide. The metal layer is prevented from reacting with the silicon of the substrate by the isolation layer in regions where no polysilicon is superjacent the metal layer, no silicide is formed, and the metal layer remains intact. Next, the metal silicide is removed with a wet etch. A metal mask remains that is essentially an exact image of the original photoresist mask. The metal mask may then be utilized as an etch mask in a halogenated-plasma etch environment. Trenches may be etched to any desired depth with virtually no erosion of the metal mask. Once the trench etch is complete, the metal etch mask may be stripped utilizing a wet reagent such as aqua regia. As a note of explanation, it should be stated that a metal mask may not be successfully created by directly etching a photoresist-masked metal layer with an aqua regia solution because of the undercutting of the metal layer that would invariably accompany such an etch. Undercutting may also be exacerbated by lifting of the photoresist in the presence of such a reagent. The more the metal layer is undercut, the more the desired pattern is distorted.
Although the Cathey-Doan process may be successfully used to replace silicon dioxide masks in conventional masking operations which use photoresist to directly pattern silicon dioxide that is subsequently used in a halogenated-plasma environment to etch trenches, it is not directly applicable to the Lowrey-Chance reduced-pitch masking process. Nevertheless, a metal masking process applicable to the Lowrey-chance process holds the promise of elimination of asymmetrical mask stringers, combined with the ability to etch deep trenches that will certainly be required for optimum bitline signal strength in a DRAM array created using those reduced-pitch masking techniques.